This invention relates to a thin film field effect transistor and a method of its manufacture, aimed at improving the characteristics of the transistor and an integrated circuit utilizing the same.
A thin film field effect transistor (FET) typically consists of source and drain electrodes interconnected by semiconductor material. Conduction between the drain and source electrodes occurs basically within the semiconductor, and the length between the source and drain is the conduction channel. Thin film field effect transistors are widely used in systems where it is desirable to have relatively high output currents and high-speed operations referred to as the operating frequency. These two depend largely on the length of the current conduction channel. In particular, the output current is inversely proportional to the channel length, while the operating frequency is inversely proportional to the square of the channel length.
The basic metal-oxide-semiconductor field-effect transistor (MOSFET) structure has a so-called xe2x80x9cflat designxe2x80x9d, as illustrated in FIG. 1. A FET structure 1 is a four-terminal device and consists of a p-type semiconductor substrate 2, into which two n-regions 3, a source electrode 4 and drain electrode 5 are formed (e.g., by ion implantation). The metal contact on the insulator is called gate 6. Heavily doped polysilicon or a combination of silicide and polysilicon can also be used as the gate electrode. The basic device parameters are the channel length L, which is the distance between the two metallurgical n-p junctions, the channel width W, the gate oxide thickness t, the junction depth, and the substrate doping. When voltage is applied to the gate, the source-to-drain electrodes correspond to two p-n junctions connected back to back. The only current that can flow from source to drain is the reverse leakage current. When a sufficiently positive bias is applied to the gate so that a surface inversion layer (or channel) is formed between the two n-regions, the source and the drain are connected by the conducting surface of the n-channel through which a large current can flow. The conductance of this channel can be modulated by varying the gate voltage. This back surface contact (or substrate contact) can have the reference voltage or be reverse-biased: the back surface voltage will also affect the channel conductance.
It is a constant trend of the industry towards higher integration, higher operation frequency, low energy consumption and lower production costs. Those goals were achieved by the constant reduction of the lithographic base line, whose width determines the channel length, the source and drain portals, the conductor""s cross-section dimension, and, in brief, the size of the transistor. The gate length determines the frequency or speed of operation, which is strictly dependent on lithographic skill. The state of the art is a line of 180 nm width.
This shrinking in size forced the transistors to be in very close proximity to each other on the flat wafer of silicon. This high density of devices raised some serious problems, including cross-talk between adjacent devices; heating of the chip at operation because of the high frequency along with a high length-to-width ratio of conduction lines and channels; high production costs caused by extremely strict demands for a very clean room and sophisticated photolithography equipment. These problems limit the present fabrication technology.
To solve the above problems, the following solutions were achieved in the art: The use of X-ray or e-beam lithography enables to obtain high integration, however it lacks industrial performance. High frequency is achieved by reducing the gate length with a vertical channel structure. This concept is disclosed in U.S. Pat. Nos. 5,340,759; 5,739,057; 5,780,327; 5.757,038. The best result of about 30 nm gate length can be achieved by the technique disclosed in U.S. Pat. No. 5,757,038, wherein selective wet etching procedures are induced on different semiconductor materials, while the substrate is a semiconductor. By enlarging the width-to-length ratio, low energy consumption can be obtained. This is accomplished by dual gate structure also disclosed in the above patents. The best result for a width-to-length ratio of about 50 can be achieved by the technique disclosed in U.S. Pat. No. 5,757,038. With regard to U.S. Pat. No. 5,340,759, is can be calculated using the parameters indicated therein that this technique could provide an even higher width-to-length ratio (about 80). However, it utilizes a design of silicon wafer on an insulator substrate, and a thin gate channel is produced by an epitaxial process at 750xc2x0 C. Moreover, Chemical Vapor Deposition is used for applying polysilicon to form a drain layer. The thickness of the thin gate oxide is about 60A.
There is accordingly a need in the art to improve the manufacture of FET and its structure to provide better operational characteristics of the FET and an electronic circuit utilizing the same.
The present invention provides a FET structure that enables to obtain a larger width-to-length ratio of the semiconductor channel (as compared to the conventional FET structure), having increased operational frequency and low energy consumption. The FET structure of the invention is characterized by sharp-phase edges of p-n junction layers, thereby improving the performance of the semiconductor device. The FET structure enables a significant reduction in cross-talk between two locally adjacent FETs.
A method of manufacturing FETs according to the invention allows for providing a vertically arranged array of FETs, thereby enabling a large number of FETs within the same footprint. The method allows for significantly simplifying the requirements of the manufacture of FET, namely eliminating the need for a xe2x80x9cclean roomxe2x80x9d, allowing low temperature conditions, and reducing the number of fabricating steps.
The main idea of the present invention consists of the following: A FET according to the invention is in the form of a conical-shaped structure, which is made in an insulator layer, and has its tip in contact with a lower electrode (source or drain) layer, preferably located in the interior of this layer. A semiconductor channel is defined by a super structure of semiconductor layers (of n-p-n or p-n-p type), occupying a periphery region of the cone, thereby providing a desirably large width-to-length ratio of the channel. A central region of the cone is a gate electrode on a gate oxide layer. The uppermost electrode (drain or source) is associated with the cone base at least partly covering the uppermost semiconductor layer. The entire FET-structure is surrounded by an insulator.
The FET according to the invention utilizes Semiconductor-on-Insulator or Metal-on Insulator technology to form a structure of the source/drain electrode on an insulator substrate, which is then covered by the insulator layer carrying another layer of active devices.
There is thus provided according to one aspect of the invention, a FET comprising a source electrode, a drain electrode, a gate electrode on a gate oxide, and a semiconductor channel, wherein
a lower one of the source and drain electrodes is formed in a groove made in the surface of an insulator substrate;
the semiconductor channel is defined by a super structure of semiconductor layers located within a periphery region of a conical-shaped structure which is immersed in an insulator layer located above the lower electrode, the tip of the conical-shaped structure being in contact with said lower electrode;
said gate electrode on the gate oxide is located within a central region of said conical-shaped structure; and
the other, upper one of the source and drain electrodes is associated with the base of said conical-shaped structure extending in a plane parallel to said lower electrode.
A plurality of such transistors forming an active layer of second semiconductor devices can be vertically arranged, being separated by insulator.
To manufacture the above FET-structure, all operations (being low temperature operations) are performed in a high vacuum chamber. A groove is formed in the surface of an, insulator substrate, e.g., SiO2, by Lithography and Plasma Etching. The groove is filled with at least one electrically or light conductive material (semiconductor and/or metal), serving as the lower electrode (source or drain), by deposition. The surface of the entire structure (the substrate-with-electrode) is polished by Ion Beam Polishing, to remove the residuals of the conductive material, and a further insulator layer is deposited thereon by Physical or Chemical Vapor Deposition. A conical-shaped pit is cut off through the upper insulator layer, in such a manner that the tip of the pit is in contact with the lower electrode (located in the interior thereof or directly thereabove). The layers of the semiconductor super structure are sequentially deposited into the pit, by CVD or PVD techniques, for example Molecular Beam Epitaxy, Ion Deposition, Cluster Beam Deposition, Ion Assisted Evaporation, etc. Then, a conical shaped opening is produced in the conical shaped pit filled with the semiconductor layers, and its walls are covered with an insulator gate oxide in which the gate electrode is then formed.
Thus, according to another aspect of the present invention, there is provided a method of fabricating FET having a source electrode, a drain electrode, a gate electrode on a gate oxide, and a semiconductor channel, the method utilizing low temperature processes conducted in a high vacuum chamber, and comprising the steps of:
(a) forming a lower one of the source and drain electrodes in a groove made in the surface of an insulator substrate;
(b) polishing the surface of a structure obtained in step (a);
(c) forming an insulator layer on the surface of the polished structure;
(d) forming a substantially conical-shaped structure in said insulator layer, having its tip portion in contact with said lower electrode, wherein a periphery region of said conical-shaped structure is a super structure of semiconductor layers defining said semiconductor channel, and a central region of said cone is said gate electrode on the gate oxide;
(e) forming the other, upper one of said source and drain electrodes at least partly extending in a plane parallel to said lower electrode;
(f) polishing the surface of a structure obtained in step (e);
(g) covering the entire surface of the polished structure obtained in step (e) by a field oxide layer.
Preferably, the formation of the conical-shaped structure comprises the following steps:
forming a substantially conical-shaped pit in the insulator layer and the lower electrode, such that the tip of the cone is in contact with the lower electrode;
sequentially depositing into said conical-shaped pit semiconductor materials from which said semiconductor channel is to be formed, so as to form a stack structure inside the pit;
forming a substantially conical-shaped opening in said stack structure, thereby forming said super structure located within the periphery region of said conical-shaped pit;
forming said gate electrode on the gate oxide inside said conical-shaped opening.
The insulator layer underlying the upper electrode also covers surface regions surrounding the conical-shaped structure. To form the upper electrode, this insulator layer is patterned to form a groove from the uppermost semiconductor layer away from the conical-shaped structure. This groove is then filled with the upper electrode material.
Obviously, the above method can be used for fabricating an array of horizontally arranged transistors. To form an array of vertically arranged transistors, the entire structure obtained in step (g) is polished, and steps (a) to (g) are repeated.
Preferably, the method also comprises the step of depositing diamond and metal layers on the entire surface of the field-oxide covered and polished structure. The presence of these layers enables the heat dissipation and the grounding of a static charge.